v 20100214 2
C 40000 40000 0 0 0 title-B.sym
T 54100 40100 9 10 1 0 0 0 1
Clif Cox
C 40000 40000 0 0 0 title-B.sym
T 50100 40700 9 10 1 0 0 0 1
Oneshot test circuit
T 54100 40100 9 10 1 0 0 0 1
Clif Cox
C 49400 44500 1 0 0 vpwl-1.sym
{
T 49300 45350 5 10 1 1 0 0 1
refdes=V1
T 50100 45350 5 10 0 0 0 0 1
device=vpwl
T 50100 45550 5 10 0 0 0 0 1
footprint=none
T 47400 44950 5 10 0 1 0 0 1
value=pwl(0 0 0.5 5 1 0) r=0
}
C 51100 46600 1 270 0 resistor-1.sym
{
T 51500 46300 5 10 0 0 270 0 1
device=RESISTOR
T 51400 46400 5 10 1 1 270 0 1
refdes=R3
T 51300 46500 5 10 1 1 0 0 1
value=10k
}
N 50900 46600 51200 46600 4
{
T 50900 46700 5 10 1 1 0 0 1
netname=Out
}
C 49400 45700 1 0 0 oneshot-1.sym
{
T 49650 46925 5 10 0 0 0 0 1
device=Oneshot
T 50000 46750 5 10 1 1 0 0 1
refdes=A1
T 50200 47050 5 10 1 1 0 5 1
value=pulse1
T 49400 45700 5 10 0 0 0 0 6
model=cntl_array = [0 5]
+ pw_array=[0 50m] retrig=FALSE
+ clk_trig = 0.5 pos_edge_trig = TRUE
+ out_low = 0.0 out_high = 5
+ rise_time=1e-9  fall_time=1e-9
+ rise_delay=1e-9 fall_delay=1e-9
T 49400 45700 5 10 0 0 0 0 1
type=oneshot
}
C 48700 45700 1 0 0 vpulse-1.sym
{
T 48300 46350 5 10 1 1 0 0 1
refdes=V2
T 49400 46550 5 10 0 0 0 0 1
device=vpulse
T 49400 46750 5 10 0 0 0 0 1
footprint=none
T 48300 47250 5 10 0 1 0 0 1
value=PWL(0 5 2m 5 2.01m 0 4m 0 4.01m 5 50m 5 50.01m 0 100m 0) r=0
}
N 49000 46900 49400 46900 4
{
T 49000 47000 5 10 1 1 0 0 1
netname=Clock
}
N 49000 45700 49400 45700 4
N 49400 45700 49400 46000 4
N 50000 45700 50000 44500 4
N 49000 44500 51200 44500 4
N 49000 44500 49000 45700 4
C 49500 44200 1 0 0 gnd-1.sym
N 50600 44500 50600 45700 4
N 50900 46000 50900 44500 4
N 50300 45700 50300 44500 4
N 51200 44500 51200 45700 4
N 49400 46900 49400 46600 4